In the field of design of integrated circuits, a counter is one of the commonest circuit devices. Counters constructed by a register and counters constructed by an on-chip Random Access Memory (RAM) are generally common.
Wherein, each of the counters constructed by the register may respond to a plurality of counting application sources, the refreshing rate of each counter is high, and refreshing may be conducted once within a clock period (1 count/clk). But, it is disadvantageous in that the register in chip design is high in cost, and thus not suitable for large-scale application.
As for the counters constructed by the on-chip RAM, a counter having large-scale counting entries may be constructed. Since the cost of the on-chip RAM is relatively low, a statistical counting RAM of few or even dozens of K is often used in a current chip. Currently, the counter constructed by the on-chip RAM conducts counting generally by using the following steps: selecting entries needing to be counted from an RAM, and reading a previous count value; then executing an addition or subtraction operation on the read count value and an applied counting step length to obtain a current counting result; and then writing the current counting result into a corresponding entry in the RAM.
From the abovementioned steps, it can be discovered that this group of counting entries must share the same group of counting application sources, and one of the entries in the RAM must be counted. So, in view of a circuit time sequence, it needs at least four beats (i.e., four clock periods) to complete the counting operation. Though the processing rate may be increased by utilizing a pipelining technology, it is necessary to take read-write performance limitation of the RAM device into consideration.
In conclusion, there is a lack of an economical and rapid counter capable of responding to a counting application for a plurality of counting entries currently.